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efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 2 mbit (256k x 8) 5v only cmos flash memory 1. features z single supply voltage 5v 10% z fast access time: 70/90 ns z compatible with jedec standard - pin-out, packages and software commands compatible with single-power supply flash z low power consumption - 25ma maximum active current - 25ua typical standby current ? z 100,000 program/erase cycles ? typically z command register architecture - byte programming (10us typical) - sector erase( sector st ructure: 16kb, 8kb, 8kb, 96kb, 128kb ) ? z auto erase (chip & sector) and auto program - sector erase and chip erase. - automatically program and verify data at specified address z end of program or erase detection - data polling - toggle bits z boot sector architecture - u = upper boot sector z packages available: - 32-pin pdip - 32-pin plcc 2. ordering information part no boot speed package part no boot speed package f49b002ua-70d upper 70 ns pdip f49b002ua-90d upper 90 ns pdip F49B002UA-70N upper 70 ns plcc f49b002ua-90n upper 90 ns plcc 3. general description the f49b002ua is a 2 megabit, 5v only cmos flash memory device organized as 256k bytes of 8 bits. this device is packaged in standard 32-pin pdip and 32-pin plcc. it is designed to be programmed and erased both in system and can in standard eprom programmers. with access times of 70 ns and 90 ns, the f49b002ua allows the operation of high-speed microprocessors. the device has separate chip enable ce , write enable we , and output enable oe controls. efst's memory devices reliably store memory data even after 10,000 program and erase cycles. the f49b002ua is entirely pin and command set compatible with the jedec standard for 2 megabit flash memory devices. commands are written to the command register using standard microprocessor write timings. the f49b002ua features a se ctor erase architecture. the device memory array is divided into 16 kbytes, 8k bytes, 8kbytes, 96kbytes, 128kbytes. erase capabilities provide the flexibility to revise the data in the device. a low v cc detector inhibits write operations on loss of power. end of program or er ase is detected by the data polling of dq7, or by the togg le bit feature on dq6. once the program or erase cycle has been successfully completed, the device internally resets to the read mode. revision: 1.4 1/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 4. pin configurations 4.1 32-pin pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd we a17 a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 32-pin dip 4.2 32-pin plcc 5 6 7 8 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 32 31 30 14 15 16 17 18 19 20 4 3 2 1 a17 we v cc nc a16 a15 a12 4.3 pin description symbol pin name functions a0~a17 address input to provide memory addresses. dq0~dq7 data input/output to output data when read and receive data when write. the outputs are in tri-state when oe or ce is high. ce chip enable to activate the device when ce is low. oe output enable to gate the data output buffers. we write enable to control the write operations. nc no connection unconnected pin v cc power supply to provide power gnd ground revision: 1.4 2/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 5. sector structure table 1: f49b002ua sector address table sector address sector sector size (kbytes) address range a17 a16 a15 a14 a13 sa4 16 3c000h-3ffffh 1 1 1 1 x sa3 8 3a000h-3bfffh 1 1 1 0 1 sa2 8 38000h-39fffh 1 1 1 0 0 sa1 96 20000h-37fffh 1 x x x x sa0 128 00000h-1ffffh 0 x x x x 6. functional block diagram g n d s t a t e c o n t r o l c e o e w e d e c o r d e r v d d a [ 1 7 : 0 ] b4 ( boot ) 16k b3 ( pa r am.1 ) 8k b2 ( pa r am.2 ) 8k b1 ( main1 ) 96k b0 ( main2 ) 128k 3ffff 3c000 3bfff 3 a 000 39fff 38000 37fff 20000 1ffff 00000 i / o bu f f e r s d q [ 7 : 0 ] revision: 1.4 3/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 7. functional description 7.1 device operation this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the register is composed of latches that store the command, address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the f49b002ua features various bus operations as table 2. table 2. f49b002ua operation modes selection address description ce oe we a17 | a13 a12 | a10 a9 a8 | a7 a6 a5 | a2 a1 a0 dq0~dq7 read l l h ain dout write l h l ain din output disable l h h x high z standby h x x x high z auto-select see table 3 notes: 1. l= logic low = v il , h= logic high = v ih , x= don't care, sa= sector address, ain= address in, din = data in, dout = data out. table 3. f49b002ua auto-select mode (high voltage method) address dq0~dq7 description ce oe we a17 | a13 a12 | a10 a9 a8 | a4 a6 a3 a2 a1 a0 l l h x x v id x x l h l l 7fh l l h x x v id x x h l l l 7fh l l h x x v id x x h h l l 7fh (manufacturer id:efst) l l h x x v id x x l l l l 8ch (device id: f49b002ua) l l h x x v id x x l l l h 00h notes : 1.manufacturer and device codes may also be accesse d via the software command sequence in table 4. 2. v id =11.5v to 12.5v. revision: 1.4 4/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 read mode to read array data from the outputs, the system must drive the ce and oe pins to v il . ce is the power control and selects the device. oe is the output control and gates array data to the output pins. we should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor?s read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?read command? section for more information. refer to the ac read operations table 9 for timing specifications and to figure 5 for the timing diagram. i cc1 in the dc characteristics table 8 represents the active current specification for reading array data. write mode to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), t he system must drive we and ce to v il , and oe to v ih . the ?program command? section has details on programming data to the device using standard command sequences. an erase operation can eras e one sector, or the entire device. table 1 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?software command definitions? section has details on erasing a sector or the entire chip. when the system writes the auto-select command sequence, the device enters the auto-select mode. the system can then read auto-select codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the auto-select mode and auto-select command sections for more information. i cc2 in the dc characteristics table 8 represents the active current specification for the write m ode. the ?ac characteristics? section contains timing specification table 10 and timing diagrams for write operations. resetting the device the reset command returns the device to read mode. this is a necessary step after reading the device or manufacturer id. note: in these cases, if vid is removed from the a9 pin, the device automatically returns to read mode and an explicit is not required. boot block looking to keep any system kernel code secure in the boot block, the f49b002ua provides a command to lock the boot block and prevent any accidental erasure or reprogramming. the command sequence is similar to the chip erase sequence except for the last cycle, where 40h must be written into dq0~dq7 instead of 10h. the boot block is the only block that can be locked in this way. whether or not the boot bl ock has been locked can be detected by the command sequence shown in table 4. this command sequence returns a ?1? on dq0 if the boot block is locked; a ?0? if the boot block has not been locked and it is open to erasing and programming. output disable mode with the oe is at a logic high level (v ih ), outputs from the devices are disabled. this will cause the output pins in a high impedance state standby mode when ce held at v cc 0.3v, the device enter cmos standby mode. if ce held at v ih , but not within the range of v cc 0.3v, the device will still be in the standby mode, but the standby current will be larger. if the device is deselected during auto algorithm of erasure or programming, the device draws active current i cc2 until the operation is completed. i cc3 in the dc characteristics table 8 represents the standby current specification. the device requires standard access time (t ce ) for read access from either of these standby modes, before it is ready to read data. revision: 1.4 5/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 auto-select mode the auto-select mode provides manufacturer and device identification and sect or protection verification, through outputs on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the auto-select codes can also be accessed in-system through the command register. when using programming equipment, this mode requires v id (11.5 v to 12.5 v) on address pin a9. while address pins a3, a2, a1, and a0 must be as shown in table 3. to verify sector protection, all necessary pins have to be set as required in table 3, the programming equipment may then read the corresponding identifier code on dq7-dq0. to access the auto-select codes in-system, the host system can issue the auto-select command via the command register, as shown in table 4. this method does not require v id . see ? software command definitions? for details on using the auto-select mode. 7.2 software command definitions writing specific address and data commands or sequences into the command register initiates the device operations. table 4 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the corresponding timing diagrams in the ac characteristics section. table 4. f49b002ua software command definitions 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle command bus cycles addr data addr data addr data addr data addr data addr data read (4) 1 ra rd - - - - - - - - - - program 4 5555h aah 2aaah 55h 5555h a0h pa pd chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h boot block lock 6 5555h aah 2 aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 40h reset 1(5) 1 xxxh f0h - - - - - - - - - - reset 2(5) 3 5555h aah 2aaah 55h 5555h f0h - - - - - - auto-select see table 5. notes: 1. x = don?t care ra = address of memory location to be read. rd = data to be read at location ra. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector. 2. except read command and auto-select command, all command bus cycles are write operations. 3. address bits a17?a16 are don?t cares. 4. no command cycles required when reading array data. 5. the two reset command sequences have exactly th e same effect, two are provided to meet the requirements of difference companies and a range of applications. revision: 1.4 6/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 revision: 1.4 7/33 table 5. f49b002ua auto-select command 1 st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle command bus cycles addr data addr data addr data addr data addr data addr data 4 5555h aah 2aaah 55h 5555h 90h xx04h 7fh - - - - 4 5555h aah 2aaah 55h 5555h 90h xx08h 7fh - - - - 4 5555h aah 2aaah 55h 5555h 90h xx0ch 7fh - - - - manufacture id 4 5555h aah 2aaah 55h 5555h 90h xx00h 8ch - - - - device id, upper boot 4 5555h aah 2aaah 55h 5555h 90h xx01h 00h - - - - notes : 1. the fourth cycle of the auto- select command sequence is a read cycle.
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 revision: 1.4 8/33 read command the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. see the ?read mode? in the ?read operations? section for more information. refer to ac read operation table 9. & figure 5 for the timing diagram. program command the program command sequence programs one byte into the device. programming is a four-bus-cycle operation. the program comm and sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7 and dq6. see ?write operation status? section for more information on these status bits. any commands written to the device during the embedded program algorithm are ignored. the program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit can?t be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is st ill ?0?. only erase operations can convert a ?0? to a ?1?. chip erase command chip erase is a six-bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity. the system can determine the status of the erase operation by using dq7 or dq6, see ?programming & erasing operation status? section for more information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. s ee the erase/program operations table 10,11 in ?ac characteristics? for parameters. sector erase command sector erase is a six-bus c ycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the sy stem can determine the status of the erase operat ion by using dq7, dq6 (refer to ?programming & erasing operation status? section for more information on these status bits.) refer to the erase/program operations table 10,11 in the ?ac characteristics? section for parameters.
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 auto-select command the auto-select command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 5 shows the address and data requirements. this method is an alternative to that shown in table 3, which is intended for prom programmers and requires v id on address bit a9. the auto-select command sequence is initiated by writing two unlock cycles, followed by the auto-select command. the device then enters the auto-select mode, and the system may read at any address any number of times, without initiating another command sequence. the read cycles at address 04h, 08h, 0ch, and 00h retrieves the efst manufacturer id. a read cycle at address 01h retrieves the device id. . 7.3 programming & erasing operation status the device provides several bits to determine the status of a programming & erasing operation: dq7, dq6, table 6 and the following subsections describe the functions of these bits. dq7, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. table 6. write operation status operation dq7 (note1) dq6 embedded program algorithm 7 dq toggle sector erase 0 toggle standard mode embedded erase algorithm chip erase 0 toggle notes: 1. dq7 require a valid address when reading status info rmation. refer to the appropriate subsection for further details. dq7: data polling during a programming operation, dq7 returns the complement of the programmed value. during an erase operation, a ?0? is produced on dq7, with this switching to a ?1? following the operation. on completion of a programming operation, reading the device after the rising edge of the last ? the sixth - write enable ( we ) pulse, returns the value just programmed (?0?) on dq7. if oe is asserted low before the operation is completed, the value of dq7 many change and it may not represent the correct value. the correct value will be return on the next read cycle, after the system has detected that the value has changed from its complement to the actual value. figure 14: data polling flow chart opposite illustrates the actual process. relevant signal pulse timings are given in figure 16 : data polling timing diagram. dq6:toggle bit i during program and erase operations, the toggle bit on dq6 switches between ?0? and ?1? on successive bus read attempts at any address. the toggling can be detected after the last risi ng edge of the write enable ( ___ we ) pulse of an erase or program command sequence and is terminated when the operation is completed. in the case of programming, the last write enable pulse is the fourth; fo r both the sector erase and chip erase commands, it is the sixth. figure 15 shows an example use of this func tion. relevant signal pulse timings are given in figure 17: toggle bit timing diagram. revision: 1.4 9/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 7.4 more device operations hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than vlko, the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the c ontrol pins to prevent unintentional writes when v cc is greater than v lko . write pulse "glitch" protection noise pulses of less than 15 ns (typical) on ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected between its v cc and gnd. power-up sequence the device powers up in the read mode. in addition, the memory contents may only be altered after successful completion of the predefined command sequences. power-up write inhibit if we = ce = v il and oe = v ih during power up, the device does not accept commands on the rising edge of we . the internal state machine is automatically reset to reading array data on power-up. revision: 1.4 10/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 8. absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . .. . . . . . . . . . . 0 c to +70 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +6.5 v a9 (note 2) ?. . . .. . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1). . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) .. . .. 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. duri ng voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 1. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 2. 2. minimum dc input voltage on pins a9 is -0.5 v. during voltage transitions, a9 may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 1. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a ti me. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 1. maximum negative overshoot waveform +0.8v -0.5v -2.0v 20ns 20ns 20ns figure 2. maximum positive overshoot waveform vcc +2.0v vcc +0.5v 2.0v 20ns 20ns 20ns revision: 1.4 11/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 9. operating ranges commercial (c) devices ambient temperature (ta) . . . . . . . . . . . 0c to +70c v cc supply voltages v cc for all devices . . . . . . . . . . . . . . . . . . . . .4.5 v to 5.5 v operating ranges define those limits between which the functi onality of the device is guaranteed. table 7. capacitance t a = 25c , f = 1.0 mhz symbol description conditions min. typ. max. unit c in1 input capacitance v in = 0v 6 pf c in2 control pin capacitance v in = 0v 12 pf c out output capacitance v out = 0v 12 pf 10. dc characteristics table 8. dc characteristics t a = 0c to 70c, v cc = 4.5v to 5.5v symbol description conditions min. typ. max. unit i li input leakage current v in = v ss or v cc , v cc = v cc max. - - 10 ua i lo output leakage current v out = v ss or v cc , v cc = v cc max - - 10 ua i cc1 v cc active read current ce = v il , oe = v ih, f = 5mhz - - 25 ma i cc2 v cc active write current ce = v il oe = v ih - 15 30 ma i cc3 cmos standby current ce = v cc 0.3v - 25 50 ua i cc4 ttl standby current ce = v ih - 0.2 5 ma v il input low voltage(note 1) - -0.3 - 0.8 v v ih input high voltage - 2.0 - v dd + 0.5 v v id voltage for auto-select and temporary sector unprotect v cc =5.0v 11.5 - 12.5 v v ol output low voltage i ol = 2.1ma - - 0.45 v v oh1 output high voltage(ttl) i oh = 0.4ma 2.4 - - v v lko low v cc lock-out voltage - 3.2 - - v revision: 1.4 12/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 11. ac characteristics test conditions figure 3. test setup ? ? 1.3k diodes = in3064 or equivalent +3.3v 1.8k cl = 100pf including jig capacitance cl = 30pf for f49b002ua cl device under test figure 4. input waveforms and measurement levels input 3.0v 0v 1.5v output 1.5v test points ac testing : inputs are driven at 3.0v for a logic "1" and 0v for a logic "0" input pulse rise and fall times are < 5ns. revision: 1.4 13/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 11.1 read operation ta = 0c to 70c, v cc = 4.5v~5.5v table 9. read operations -70 -90 symbol description conditions min. max. min. max. unit t rc read cycle time (note 1) 70 90 ns t acc address to output delay ce = oe = v il 70 90 ns t ce ce to output delay oe = v il 70 90 ns t oe oe to output delay ce = v il 30 35 ns t df oe high to output float (note1) ce = v il 25 30 ns t oeh output enable read 0 0 ns hold time toggle and data polling 10 10 ns t oh address to output hold ce = oe = v il 0 0 ns notes : 1. not 100% tested. 2. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven. figure 5. read timing waveform t rc addresses stable output valid address high-z ce we oe outputs high-z t acc t oeh t oe t oh t df t ce revision: 1.4 14/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 11.2 program/erase operation table 10. we controlled program/erase operations( t a = 0c to 70c, v cc = 4.5v~5.5v ) -70 -90 symbol description min. max. min. max. unit t wc write cycle time (note 1) 70 90 ns t as address setup time 0 0 ns t ah address hold time 45 45 ns t ds data setup time 30 30 ns t dh data hold time 0 0 ns t oes output enable setup time 0 0 ns t ghwl read recovery time before write ( oe high to we l ow) 0 0 ns t cs ce setup time 0 0 ns t ch ce hold time 0 0 ns t wp write pulse width 35 35 ns t wph write pulse width high 20 20 ns notes : 1. not 100% tested. 2. see the "programming & erasing operation performance" section for more information. revision: 1.4 15/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 table 11. ce controlled program/erase operations(t a = 0c to 70c, v cc = 4.5v~5.5v) -70 -90 symbol description min. max. min. max. unit t wc write cycle time (note 1) 70 90 ns t as address setup time 0 0 ns t ah address hold time 45 45 ns t ds data setup time 35 35 ns t dh data hold time 0 0 ns t oes output enable setup time 0 0 ns t ghel read recovery time before write 0 0 ns t ws we setup time 0 0 ns t wh we hold time 0 0 ns t cp ce pulse width 35 35 ns t cph ce pulse width high 30 30 ns t whwh1 programming operation(note2 ) 10(typ.) 10(typ.) us t whwh2 sector erase operation (note2) 1.5(typ.) 1.5(typ.) sec notes : 1. not 100% tested. 2. see the "programming & erasing operation performance" section for more information. revision: 1.4 16/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 6. ce controlled program timing waveform address we ce oe 5555 for program 2aaa for erase data polling t as t wc pd data pa for program sa for sector erase 5555 for chip erase a0 for program 55 for erase pd for program 30 for sector erase 10 fo r chi p e r ase t wh t ah t ds t dh t ghel t cp t cph t busy t ws dout dq7 t whwh1 or 2 notes : 1. pa = program address, pd = program data, dout = data out , dq7 = complement of data written to device 2. figure indicates the last two bus cycles of the command sequence.. revision: 1.4 17/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 7. write command timing waveform oe data v ih v il add valid v ih v il v ih v il v ih v il v ih v il t ah t as t wp t wph vcc 5v address we ce t cwc t cs t ch t dh t ds din t oes revision: 1.4 18/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 8. embedded programming timing waveform address ce we oe 5555 for program 2aaa for erase data polling t as t wc pd data pa for program sa for sector erase 5555 for chip erase a0 for program 55 for erase pd for program 30 for sector erase 10 fo r chi p e r ase t ch t ah t ds t dh t ghwl t wp t wph t busy t cs dout dq7 t whwh1 or 2 notes : 1. pa = program address, pd = program data, dout = data out , dq7 = complement of data written to device 2. figure indicates the last two bus cycles of the command sequence.. revision: 1.4 19/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 9. embedded programming algorithm flowchart start write data aah address 5555h verify work ok? embedded program completed data poll from system yes last address? yes no write data 55h address 2aaah write data a0h address 5555h no increment address write data pd address pa revision: 1.4 20/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 revision: 1.4 21/33 12. programming & erasing operation performance table 12. erase and programming performance (note.1) limits parameter typ.(2) max.(3) unit sector erase time 1.5 5 sec chip erase time 3 35 sec byte programming time 10 200 us chip programming time 2 5 sec erase/program cycles (1) 100,000 - cycles notes: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25c, 5v. 3.maximum values measured at 85c, 4.5v.
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 10. embedded chip erase timing waveform address ce we oe 2aaah 5555h va va t wc t as erase command sequence(last two cycle) read status data t ah t ch t ghwl t wp t cs t wph 55h t ds t dh 10h in progress complete t whwh2 data t vcs v cc notes : sa = sector address (for sector erase, va = valid address for reading status data (see "write operation status") revision: 1.4 22/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 11. embedded chip erase algorithm flowchart start write data aah address 5555h embedded chip erease completed data = ffh? yes no write data 55h address 2aaah write data 80h address 5555h write data aah address 5555h write data 55h address 2aaah write data 10h address 5555h data polling from system revision: 1.4 23/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 12. embedded sector erase timing waveform ce we address oe 2aaah sa va va t wc t as erase command sequence(last two cycle) read status data t ah t ch t ghwl t wp t cs t wph 55h t ds t dh 30h in progress complete t whwh1 data t vcs vcc notes : sa = sector address (for sector erase, va = valid address for reading status data (see "programming & erasing operation status") revision: 1.4 24/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 13. embedded sector erase algorithm flowchart start write data aah address 5555h embedded sector erease completed yes write data 55h address 2aaah write data 80h address 5555h write data aah address 5555h write data 55h address 2aaah write data 30h address sa data poll from system data = ffh? no revision: 1.4 25/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 programming & erasing operation status figure 14. data polling algorithm start read dq7~dq0 add. = va(1) dq7 = data? pass no yes notes : 1. va =valid address for programming. revision: 1.4 26/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 15. toggle bit algorithm start read dq7~dq0 read dq7~dq0 toggle bit = dq6 toggle? pass yes no (note1) note : 1. read toggle bit twice to determi ne whether or not it is toggle. revision: 1.4 27/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 16. data polling timings (during embedded algorithms) we address ce oe t acc dq7 t ce va va t rc t oe t oeh t ch t df t oh complement complement true vaild data high-z status data status data true vaild data high-z dq0~dq6 t whwh1 or t whwh2 notes : va = valid address. figure shows first status cycle af ter command sequence, last status read cycle, and array data read cycle. revision: 1.4 28/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 17. toggle bit timing wavefo rms (during embedded algorithms) address ce oe we t acc dq6 t ce va va t rc t oe t oeh t ch t df t oh vaild status va vaild status va high-z (fi rst re ad ) (second read) vaild data (stops toggling) vaild data t whwh1 or t whwh2 notes : va = valid address; not required for dq6. figure shows first status cycle after command sequence, last status read cycle, and array data read cycle. revision: 1.4 29/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 figure 18. id code read timing waveform add a2~a8 a10~a18 ce we oe v ih v ih v ih v il v il v il v ih v il v ih v il v ih v il v ih v il v cc 5v t acc t ce t acc v id t oe add a9 add a0 a1 data dq0~dq7 v ih v il t oh t oh t df data out 00h data out 7fh revision: 1.4 30/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 12. package dimension 32-lead pdip 32 17 16 1 d e 1 a l 2 a a 1 e b b 1 e c e a dimension in inch dimension in mm min norm max min norm max a ------- ------- 0.210 ------- ------- 5.33 a 1 0.015 ------- ------- 0.381 ------- ------- a 2 0.149 0.154 0.159 3.785 3.912 4.039 b 0.018 typ 0.457 typ b1 0.050 typ 1.270 typ c ------- 0.010 ------- ------- 0.254 ------- e 0.590 ------- 0.625 14.986 ------- 15.875 e 1 0.530 ------- 0.560 13.462 ------- 14.224 e a 0.600 bsc 15.240 bsc l 0.120 ------- 0.150 3.048 ------- 3.810 e 0.100 typ 2.540 typ ------- 15 o ------- 15 o revision: 1.4 31/33
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 32-lead plcc revision: 1.4 32/33 d d 1 e 1 e a 0.020" min symbol dimension in mm dimension in inch min norm max min norm max a 3.18 ------- 3.55 0.125 ------- 0.140 a 1 1.53 ------- 2.41 0.060 ------- 0.095 a 2 2.79 ref 0.110 ref b 0.33 ------- 0.54 0.013 ------- 0.021 b2 0.66 ------- 0.82 0.026 ------- 0.032 c 0.20 ------- 0.36 0.008 ------- 0.014 e 1.27 bsc 0.050 bsc 0 o ------- 10 o 0 o ------- 10 o e 14.86 14.99 15.11 0.585 0.590 0.595 e 1 13.90 13.97 14.04 0.547 0.550 0.553 e 2 6.05 ------- 6.93 0.238 ------- 0.273 e 3 10.16 bsc 0.400 bsc d 12.32 12.45 12.57 0.485 0.490 0.495 d 1 11.36 11.43 11.50 0.447 0.450 0.453 d 2 4.78 ------- 5.66 0.188 ------- 0.223 d 3 7.62 bsc 0.300 bsc seating plane 0.004 2 d -c- e 2 -c- 1 a 14 20 13 5 4 21 32 1 30 29 d 2 o e 2 e b b 2 c d 3 e 3 a 2
efst f49b002ua elite flash storage technology inc. publication date : sep. 2006 revision: 1.4 33/33 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of efst. the contents contained in this docu ment are believed to be accurate at the time of publication. efst a ssumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the applic ation of our pr oducts. no responsibility is assumed by efst for any infringement of patents, copyrights, or other intellectual property rights of third pa rties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intell ectual property rights of efst or others. any semiconductor devices may hav e inherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeg uards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. efst 's products are not authorized for use in critical applications such as, but not limited to, life suppor t devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.

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